CMOS Gate Array Design Exercise

Simulation of OrCAD designs using Verilog

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• Perform a design rule Check on your OrCAD design.

  Select the design file and look for Design Rules Check... on the Tools menu.

  This will check for problems such as two part instances with duplicate reference names which would preclude a successful simulation.

  Correct any errors!

• Generate a verilog netlist from your OrCAD design.

  Select the design file and look for Create Netlist... on the Tools menu.

  If your design is seq.dsn the filename will default to seq.v

• Start Exceed

  To allow graphical display of the simulation

• Telnet to salvador

  TerraTerm Pro gives the best results

• Change to your OrCAD directory

  e.g. cd design_2/orcad/sequencer

• Run the simulation for your schematic.

  If your design is the simple test sequencer and your schematic is SCHEMATIC1 you should type

  simulate_orcad +simgr test SCHEMATIC1 seq.v

  Replace test with one of the following to test a different type of circuit:

  • updown - to test an updown circuit
  • button - to test a button circuit
  • counter - to test an 8 bit counter circuit without the updown unit
  • mouse - to test a full mouse circuit including an 8 bit counter
  • final - to test a full mouse circuit including an 8 bit counter

  In order to simulate a smaller counter you need to add an extra +define parameter to the command.

  To simulate a four bit counter on its own type

  simulate_orcad +simgr +define+nbits4 counter <cellname> <vfilename>

  To simulate a full mouse circuit including a 5 bit counter type

  simulate_orcad +simgr +define+nbits5 mouse <cellname> <vfilename>

• Tell me if it works....

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Notes - OrCAD simulation is only supported for circuits without breaks for testability. Names of signals must be correct for simulation to succeed. OrCAD may get the case of some names wrong!

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