------------------------------------------------------------
-- Entity and architecture for test_bench
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity test_decode is
end entity test_decode;

architecture test_bench of test_decode is

  signal CLOCK : std_logic := '1';
  signal nRESET, DATA, STROBE : std_logic;
  signal SERIAL_OUT : std_logic;
  signal segA, segB, segC, segD, segE, segF, segG, ucRESET, ramDISABLE : std_logic;
  signal data_loop : std_logic_vector(95 downto 0) :=
            "0" & "000000000" & "0000" & "00000" & "0110110" & "000101" &
            "0" & "000000000" & "0000" & "00000" & "1001001" & "000101" &
            "0" & "000000000" & "0000" & "00000" & "0000000" & "000101";
  signal strobe_loop : std_logic_vector(31 downto 0) :=
           "0" & "000000000" & "0000" & "00000" & "0000001" & "000000";

begin
  decode_inst: entity work.decode(structure) 
    port map (CLOCK, nRESET, DATA, STROBE, SERIAL_OUT,
		segA, segB, segC, segD, segE, segF, segG, ucRESET, ramDISABLE);

  CLOCK <= not clock after 500 us;
  nRESET <= '0', '1' after 100 us;
  data_loop <= data_loop(0) & data_loop(95 downto 1) after 1000 us;
  strobe_loop <=strobe_loop(0) & strobe_loop(31 downto 1) after 1000 us;

  DATA <= data_loop(0) after 1 us;
  STROBE <= strobe_loop(0) after 1 us;

end architecture test_bench;